The present invention relates to a method and/or architecture for implementing storage elements generally and, more particularly, to a method and/or architecture for implementing a master/dual-slave D type flip-flop that may choose which input is a clock input and which input is a data input.
Referring to FIG. 1, a conventional circuit 10 is shown implementing a flip-flop 12 and a flip-flop 14. The flip-flops 12 and 14 are cross-coupled. The flip-flops 12 and 14 double the load capacitance presented to the previous stage. The flip-flops 12 and 14 are triggered in response to the input signals IN1 and IN2. The circuit 10 provides one solution for selecting which input is a clock input and which input is a data input. A multiplexer 16 is implemented to select which output (Q1 or Q2) is selected. It is desirable to implement large transistors in the flip-flops 12 and 14 to provide high speed and accurate current matching. However, doubling the load of the circuit 10 is a severe disadvantage in current consumption and speed.
Referring to FIG. 2, another conventional circuit 20 with high time skew and noise is shown. The multiplexers 22 and 24 on the input paths IN1 and IN2 select which signal to present to the clock input and which signal to present to the data input of the flip-flop 26. The flip-flop 26 acts as a time discriminator for the circuit 20. However, the multiplexers 22 and 24 add extra delay and hence potential timing skew. The multiplexers 22 and 24 also need to be large to drive the large size of input transistors of the flip-flop 26. The multiplexers 22 and 24 increase jitter of the circuit 20. Furthermore, in other conventional implementations, the multiplexers 22 and 24 can be added before and/or after the flip-flop 26.
Referring to FIG. 3, a schematic of a conventional master/slave flip-flop 30 is shown. The circuit 30 may be similar to the flip-flops 12, 14 and 26. Conventional master/slave flip-flop configurations, such as the circuit 10 or the circuit 20, have one or more of the following disadvantages of requiring (i) additional circuitry for a dual load device, (ii) multiplexers on the inputs that have the potential to disrupt setup times and add skew between reference and feedback signals, and/or (iii) implementing two flip-flops in parallel which doubles the load capacitance seen by the inputs, which slows down the proceeding circuitry which increases time skews and increases susceptibility to noise.
The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to receive a first input signal and a second input signal and present a first signal and a second signal. The second circuit may be configured to present a first output signal in response to the first input signal, the first signal and the second signal. The third circuit may be configured to present a second output signal in response to the second input signal, the first signal and the second signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a flip-flop that may choose which input acts as a clock input and which input acts as a data input and may (i) provide a CMOS master/dual-slave D type flip-flop, (ii) provide functionality of two D type flip-flops connected in parallel, (iii) have reduced load capacitance, (iv) require less circuitry, (v) have minimal circuit overhead, (vi) not increase input loading over a single D flip-flop, (vii) provide symmetrical design with potentially zero input timing skew, and/or (viii) be implemented without multiplexers on the input.